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MPU RISC 32bit 650MHz 361-Pin TFBGA Tray

STM32MP1 microprocessor series with dual Arm® Cortex®-A7 and Cortex®-M4 Cores

A general-purpose microprocessor portfolio enabling easy development for a broad range of applications, the STM32MP1 series is based on a heterogeneous single or dual Arm Cortex-A7 and Cortex-M4 cores architecture, strengthening its ability to support multiple and flexible applications, achieving the best performance and power figures at any time. The Cortex-A7 core provides access to open-source operating systems (Linux/Android) while the Cortex-M4 core leverages the STM32 MCU ecosystem.

The STM32MP1 comes with many benefits including a rich development ecosystem:

  • • Mainlined open-source Linux distribution with Android support available via partners
  • • STM32Cube firmware and embedded software libraries for Cortex-M4 core
  • • An optional 3D graphics processing unit (GPU) provides for advanced HMI development
  • • Rich set of digital and analog peripherals
  • • Advanced security features

Features and Benefits:

STM32 ecosystem with support for open-source operating systems

Developers familiar with the Cortex®-M4 MCU environment will easily find their marks as they will be able to use the same STM32Cube toolset including GCC-based IDEs, STM32CubeProgrammer and STM32CubeMX, which includes the DRAM interface tuning tool for easy configuration of the DRAM sub-system.

When developing for the Arm® Cortex®-A7 core, ST helps eliminate potential roadblocks through the development of its mainlined open-source OpenSTLinux Distribution to ensure that porting application software is fast and easy.

Flexible architecture

The single or dual Cortex-A7 cores are dedicated to open-source operating systems while the Cortex-M4 core is dedicated to real-time and low-power tasks.

  • • Dual Cortex®-A7 cores running at 800 MHz 
    • - 32-Kbyte L1 Instruction cache
    • - 32-Kbyte L1 Data cache
    • - 256-Kbyte Level 2 cache
  • • Cortex®-M4 core running at 209 MHz
    • - a single-precision floating point unit (FPU)
    • - a full set of digital signal processor (DSP) instructions
    • - memory protection unit for enhanced application security

The Cortex-M4 core benefits from an embedded SRAM (448 Kbytes) to run purely deterministic code. For instance, a customer currently using an STM32 MCU based on STM32Cube firmware, could transparently fully re-use his code on the Cortex-M4 core’s 448 Kbytes of SRAM, and add the Linux application (for instance an HMI) running on the Cortex-A7 core(s).

To meet a broad range of applications requirements, most peripherals can be allocated to either the Cortex-A7 or Cortex-M4 cores.

Power efficiency

  • • Dynamic efficiency: Cortex-A7 and Cortex-M4 cores can be run or stopped independently to achieve the best power efficiency for each processing and real-time application requirement.
  • • Low-power modes: Multiple low-power modes are available including:
    • - Standby mode: Down to 36 µW.
    • - VBAT mode: Down to 4.5 µW. In this mode, it is possible to keep track of time using the real-time clock while keeping the system secure thanks to the tamper detect feature.

The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible:

  • • STM32MP157: Dual Cortex-A7 cores up to @ 800 MHz, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
  • • STM32MP153: Dual Cortex-A7 cores up to @ 800 MHz, Cortex-M4 core @ 209 MHz and CAN FD
  • • STM32MP151: Single Cortex-A7 core up to @ 800 MHz, Cortex-M4 core @ 209 MHz

Each line comes with a security option (cryptography & secure boot)

STM32MP1 – Family Expansion

Watch this video to discover the latest news on the STM32MP1 MPU, learn how its ecosystem is being enhanced and follow a practical demonstration based on new version of the STM32MP1 MPU.

STM32MP1 Series – Related Development Tools


See all STM32MP1 Series